# AMD Helios Helios is a rack-scale system: seventy-two accelerators and eighteen server processors across eighteen compute trays and six switch trays, in one liquid-cooled frame weighing on the order of seven thousand pounds. Its architectural significance is the route it takes to get there. Where the incumbent rack-scale platform integrates vertically around proprietary interconnect, this one is assembled from open and consortium specifications at every layer. > [!note] The one-sentence version > The same seventy-two-accelerator rack, built from open rack, open scale-up fabric and standards-aligned Ethernet rather than from one vendor's stack. ## The open-standards composition **Open rack.** Built to the industry consortium's wide-rack specification, with four-accelerator trays conforming to it, which means the mechanical, power, and thermal envelopes are published rather than proprietary; see [[wiki/OCP Accelerator Module|OCP Accelerator Module]] and [[wiki/Data Center Rack|Data Center Rack]]. **Open scale-up fabric.** Accelerator-to-accelerator memory traffic carried over the consortium fabric running on Ethernet signaling, which standardizes the memory-semantic claim that had been proprietary; see [[wiki/UALink|UALink]] and [[wiki/Scale-Up and Scale-Out|Scale-Up and Scale-Out]]. **Standards-aligned scale-out.** Rack-to-rack traffic over Ethernet aligned with the consortium work on lossless cluster behavior, rather than a purpose-built fabric; see [[wiki/Ultra Ethernet|Ultra Ethernet]]. **Open software.** The accelerator stack is open-source, with support in the major framework and the leading inference engines; see [[wiki/ROCm|ROCm]], [[wiki/PyTorch|PyTorch]], [[wiki/vLLM|vLLM]], and [[wiki/SGLang|SGLang]]. **Programmable networking** from the vendor's acquired low-latency data-plane engine; see [[wiki/Pensando|Pensando]] and [[wiki/DPU and SmartNIC|DPU and SmartNIC]]. ## What the bet is The wager is that buyers want the capability without single-vendor supply. If the socket, the rack, the scale-up fabric, the scale-out fabric, and the software are all published, then a second and third supplier can build compatible parts, an operator can mix generations and vendors, and the buyer's exit cost falls. For an operator that is price and resilience; for a country assembling compute capacity from more than one supply chain, it is strategic position; see [[wiki/Exit Cost|Exit Cost]], [[wiki/Compute Sovereignty|Compute Sovereignty]], and [[wiki/National Compute Capacity|National Compute Capacity]]. ## Disclosed specification and posture Up to 2.9 exaFLOPS at four-bit precision and 31 terabytes of high-bandwidth memory per rack, built on the current accelerator family with sixth-generation server processors; rack power in the region of 225 to 245 kilowatts, with four accelerators per processor under copper cold plates on a closed liquid loop; see [[wiki/AMD MI450|AMD MI450]], [[wiki/AMD EPYC|AMD EPYC]], [[wiki/Cold Plate|Cold Plate]], and [[wiki/Direct-to-Chip Liquid Cooling|Direct-to-Chip Liquid Cooling]]. Analyst estimates place system cost somewhat above the incumbent platform. Vendor statements on inference, memory, efficiency, and customizability advantages are vendor statements pending independent benchmarking, and the platform's availability has been tied to general availability rather than demonstrated across every configuration. ## Relationships - **built from:** [[wiki/AMD MI450|AMD MI450]] · [[wiki/AMD EPYC|AMD EPYC]] · [[wiki/Compute Tray|Compute Tray]] - **standardized on:** [[wiki/OCP Accelerator Module|OCP Accelerator Module]] · [[wiki/UALink|UALink]] · [[wiki/Ultra Ethernet|Ultra Ethernet]] - **networked by:** [[wiki/Pensando|Pensando]] - **programmed through:** [[wiki/ROCm|ROCm]] - **compared with:** [[wiki/NVIDIA NVL72|NVIDIA NVL72]] · [[wiki/NVIDIA Grace Blackwell|NVIDIA Grace Blackwell]] · [[wiki/NVIDIA Vera Rubin|NVIDIA Vera Rubin]] - **realizes:** [[wiki/Rack-Scale Computing|Rack-Scale Computing]] · [[wiki/Compute and Accelerator Systems|Compute and Accelerator Systems]] - **source articles:** [[articles/Vertically Integrating an AI Superpower from AI Factory to Citizen|Vertically Integrating an AI Superpower from AI Factory to Citizen]] · [[articles/The Gigawatt Is the New Measure of War|The Gigawatt Is the New Measure of War]] - **collection route:** [[collections/American Infrastructure|American Infrastructure]] · [[collections/American|American Collection]] ## Evidence posture - **Established:** seventy-two accelerators and eighteen server processors across eighteen compute trays and six switch trays; roughly seven thousand pounds per frame; four accelerators per processor under copper cold plates on a closed liquid loop; rack power in the region of 225 to 245 kilowatts; construction to the consortium wide-rack specification; scale-up over the consortium fabric on Ethernet with consortium-aligned Ethernet scale-out; the programmable networking engine acquired in 2022. - **Announced (not yet demonstrated across configurations):** up to 2.9 exaFLOPS at four-bit precision and 31 terabytes of high-bandwidth memory per rack; availability tied to platform general availability. - **Plausible:** analyst cost estimates placing the system somewhat above the incumbent platform; these are third-party estimates rather than disclosed prices. - **Unresolved:** vendor claims of advantage in inference, memory bandwidth, efficiency, and customizability, pending independent benchmarking. ## Sources - [Helios Is AMD's First AI System To Rival Nvidia Vera Rubin](https://www.cnbc.com/) — CNBC, October 2026; rack composition, weight, power, cooling, memory, precision, open-standards alignment, networking engine, analyst cost estimates, and vendor claims.