# AMD MI300X The MI300X is the most legible chiplet accelerator ever shipped: eight compute dies stacked above four input-output and cache dies on a silicon interposer, ringed by stacked memory, presented to software as one device. If a reader wants to see what disaggregated construction actually looks like, this is the part to look at. > [!note] The one-sentence version > Thirteen pieces of silicon in one package, behaving as a single accelerator, built around having more memory than the competition. ## The construction Compute dies are fabricated on the newest node available and stacked directly above dies carrying the memory controllers, the last-level cache, and the external interfaces, which are built on a more mature and cheaper process. Vertical connections carry traffic between the layers, and a silicon interposer beneath carries the dense wiring between the stacks and out to the memory; see [[wiki/Chiplet|Chiplet]] and [[wiki/Advanced Packaging|Advanced Packaging]]. Each die is tested before assembly, so package yield is the product of high per-die yields rather than one low monolithic yield. The architectural reward is that the expensive node is spent only on arithmetic. The architectural cost is that every crossing between dies consumes energy and adds latency, which is why the cache and interconnect design beneath the compute dies matters as much as the compute dies themselves; see [[wiki/Infinity Fabric|Infinity Fabric]]. ## The memory argument This generation competed principally on memory capacity and bandwidth rather than on peak arithmetic, on the reasoning that inference is bandwidth-bound and that a model which fits on fewer devices requires less communication; see [[wiki/Memory Wall|Memory Wall]] and [[wiki/Prefill and Decode|Prefill and Decode]]. The argument was substantially correct about the physics, and the adoption question turned on software rather than on specifications: a device is reached through compilers, kernels, collective libraries, and framework support, and that ecosystem had to be built; see [[wiki/ROCm|ROCm]] and [[wiki/CUDA|CUDA]]. This is the clearest case in the collection of hardware capability and market position diverging, and of why the industry's own analysts identify software as the decisive element. ## Relationships - **built from:** [[wiki/Chiplet|Chiplet]] · [[wiki/Advanced Packaging|Advanced Packaging]] · [[wiki/High-Bandwidth Memory|High-Bandwidth Memory]] - **interconnected by:** [[wiki/Infinity Fabric|Infinity Fabric]] - **programmed through:** [[wiki/ROCm|ROCm]] · [[wiki/PyTorch|PyTorch]] - **part of:** [[wiki/AMD Instinct GPUs|AMD Instinct]] · [[wiki/Compute and Accelerator Systems|Compute and Accelerator Systems]] - **succeeded by:** [[wiki/AMD MI350X|AMD MI350X]] · [[wiki/AMD MI450|AMD MI450]] - **source articles:** [[articles/Vertically Integrating an AI Superpower from AI Factory to Citizen|Vertically Integrating an AI Superpower from AI Factory to Citizen]] · [[articles/The Gigawatt Is the New Measure of War|The Gigawatt Is the New Measure of War]] - **collection route:** [[collections/American Infrastructure|American Infrastructure]] · [[collections/American|American Collection]] ## Evidence posture - **Established:** eight compute dies stacked above four input-output and cache dies on a silicon interposer with stacked memory, presented as a single device; heterogeneous node assignment with arithmetic on the newest process; known-good-die testing; per-crossing energy and latency costs of disaggregation; competition on memory capacity and bandwidth rather than peak arithmetic. - **Established:** published system building blocks offering this part in eight-accelerator configurations with host memory on the order of two and a third terabytes. - **Established (datestamped):** as of October 2026, independent analysts identify the software ecosystem rather than hardware capability as the decisive competitive element. ## Sources - [Helios Is AMD's First AI System To Rival Nvidia Vera Rubin](https://www.cnbc.com/) — CNBC, October 2026; the analyst assessment of hardware parity and software lead. - Public accelerator architecture documentation, as of October 2026.