# CXL **Domain:** Computer Architecture / Memory / Open Standards **Doc Type:** Technical Standard Node **Maturity:** Evolving ## Definition **CXL**, Compute Express Link, is an open coherent interconnect for processors, memory expansion and accelerators. It provides I/O, cache and memory semantics over a high-speed link so hosts and attached devices can share resources with less software-visible separation. ## Governing Boundary CXL governs the boundary between processor, accelerator and memory. Switching and fabric capabilities extend the relation beyond one fixed host-device pairing, supporting memory expansion, pooling, sharing and more composable systems. ## Higher-Order Capability Memory capacity can become a managed resource rather than a permanently stranded property of one server. That does not make all memory equally local or interchangeable; topology, coherence, latency and failure boundaries remain decisive. ## Relation to Governance CXL makes the memory map an allocation surface. Fabric managers and platform software can determine which resources become visible to which hosts, so composability creates both utilization gains and a new control layer. ## Failure Modes Coherence and sharing enlarge the domain in which faults, configuration errors and security decisions matter. Operators must preserve isolation, observability, performance predictability and safe behavior under partial failure. ## Related Ontology [[wiki/Rack-Scale Computing|Rack-Scale Computing]] · [[wiki/UALink|UALink]] · [[wiki/Composable Infrastructure|Composable Infrastructure]] · [[wiki/Control Plane|Control Plane]] · [[wiki/AI Factory|AI Factory]] ## Sources / Provenance - [CXL Consortium — About CXL](https://computeexpresslink.org/about-cxl/) - [CXL Consortium — Specifications](https://computeexpresslink.org/cxl-specification/)