CXL - Bryant McGill

# CXL **Entity class:** Concept or analytic term **Domain:** Computer Architecture / Memory / Open Standards **Doc Type:** Technical Standard Node **Maturity:** Evolving ## Definition **CXL**, Compute Express Link, is an open coherent interconnect for processors, memory expansion and accelerators. It provides I/O, cache and memory semantics over a high-speed link so hosts and attached devices can share resources with less software-visible separation. ## Governing Boundary CXL governs the boundary between processor, accelerator and memory. Switching and fabric capabilities extend the relation beyond one fixed host-device pairing, supporting memory expansion, pooling, sharing and more composable systems. ## Higher-Order Capability Memory capacity can become a managed resource rather than a permanently stranded property of one server. That does not make all memory equally local or interchangeable; topology, coherence, latency and failure boundaries remain decisive. ## Relation to Governance CXL makes the memory map an allocation surface. Fabric managers and platform software can determine which resources become visible to which hosts, so composability creates both utilization gains and a new control layer. ## Failure Modes Coherence and sharing enlarge the domain in which faults, configuration errors and security decisions matter. Operators must preserve isolation, observability, performance predictability and safe behavior under partial failure. ## Related Ontology [[wiki/Rack-Scale Computing|Rack-Scale Computing]] · [[wiki/UALink|UALink]] · [[wiki/Composable Infrastructure|Composable Infrastructure]] · [[wiki/Control Plane|Control Plane]] · [[wiki/AI Factory|AI Factory]] ## Sources / Provenance - [CXL Consortium — About CXL](https://computeexpresslink.org/about-cxl/) - [CXL Consortium — Specifications](https://computeexpresslink.org/cxl-specification/) ## Relationships  This entry is routed through [[collections/Consciousness Continuity|Consciousness Continuity]], [[collections/Neurotech|Neurotech]], and [[collections/Machine Succession|Machine Succession]]. Its source context is developed in [[articles/Mind Uploading and AI — The Host is Reusable and the Person is the Delta|Mind Uploading and AI — The Host is Reusable and the Person is the Delta]] and [[articles/Technologies for Consciousness Mapping and Transfer|Technologies for Consciousness Mapping and Transfer]]. Status-qualified source edges are preserved in the terminal Research Edges section. ### Key Relationships - [[wiki/Redfish|Redfish]] is associated with **CXL**. DMTF publishes CXL-to-Redfish mapping. ### Connections in this corpus - **CXL** is connected in the corpus with [[wiki/Computational Metabolism|Computational Metabolism]]. Memory can become a pooled fabric resource rather than fixed server-local capacity. - **CXL** is connected in the corpus with [[wiki/Receiving Substrate|Receiving Substrate]]. Memory disaggregation reduces dependence on one physical server configuration.  ## Read First in the Wiki  - [[wiki/AI Factory|AI Factory]] — supplies the related concept or analytic term context needed to place **CXL** within the wider system. - [[wiki/Composable Infrastructure|Composable Infrastructure]] — supplies the related concept or analytic term context needed to place **CXL** within the wider system. - [[wiki/Rack-Scale Computing|Rack-Scale Computing]] — supplies the related concept or analytic term context needed to place **CXL** within the wider system. - [[wiki/UALink|UALink]] — supplies the related concept or analytic term context needed to place **CXL** within the wider system.  ## Related Work in the Corpus  - In [[articles/Mind Uploading and AI — The Host is Reusable and the Person is the Delta|Mind Uploading and AI — The Host is Reusable and the Person is the Delta]], **Host-infrastructure crosswalk** provides the narrative context for **CXL**: Finally, UALink, the Ultra Ethernet Consortium, DMTF Redfish, CXL, 800 VDC AI data-center power, Maia 200, BlueField-4, and BlueField-4 STX expose the receiving substrate as an interoperable stack of fabrics, management planes,…  ## Research Edges  #### Host–residual infrastructure patch — 2026-09-10 **Collections:** [[collections/Consciousness Continuity|Consciousness Continuity]] · [[collections/Neurotech|Neurotech]] · [[collections/Machine Succession|Machine Succession]] **Canonical source article:** [[articles/Mind Uploading and AI — The Host is Reusable and the Person is the Delta|Mind Uploading and AI — The Host is Reusable and the Person is the Delta]] **Related acquisition source:** [[articles/Technologies for Consciousness Mapping and Transfer|Technologies for Consciousness Mapping and Transfer]] **Relationship source:** [[research/Mind Uploading and AI Host-Residual Ecosystem Relationship Graph - 2026-09-10|Mind Uploading and AI Host-Residual Ecosystem Relationship Graph — 2026-09-10]] #### Host-infrastructure integration This entry is expanded through the concrete host-side relationships and status-qualified edges below. #### Outgoing typed edges - **HR-0296 — `wiki_links_to` → [[wiki/AI Factory|AI Factory]]** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `CXL.md`. - **HR-0297 — `wiki_links_to` → [[wiki/Composable Infrastructure|Composable Infrastructure]]** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `CXL.md`. - **HR-0298 — `wiki_links_to` → [[wiki/Rack-Scale Computing|Rack-Scale Computing]]** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `CXL.md`. - **HR-0299 — `wiki_links_to` → [[wiki/UALink|UALink]]** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `CXL.md`. - **HR-1379 — `cross_threads` → [[wiki/Computational Metabolism|Computational Metabolism]]** — **HIGH VALUE CROSS THREAD**; evidence `ARTICLE`, `WIKI_ARCHIVE`. Memory can become a pooled fabric resource rather than fixed server-local capacity. - **HR-1380 — `cross_threads` → [[wiki/Receiving Substrate|Receiving Substrate]]** — **HIGH VALUE CROSS THREAD**; evidence `ARTICLE`, `WIKI_ARCHIVE`. Memory disaggregation reduces dependence on one physical server configuration. #### Incoming typed edges - **HR-0188 — [[wiki/DMTF Redfish|Redfish]] `maps_to` → this entry** — **VERIFIED EXTERNAL**; evidence `WEB_REDFISH`. DMTF publishes CXL-to-Redfish mapping. - **HR-0333 — [[wiki/Composable Infrastructure|Composable Infrastructure]] `wiki_links_to` → this entry** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `Composable Infrastructure.md`. - **HR-0921 — [[wiki/Rack-Scale Computing|Rack-Scale Computing]] `wiki_links_to` → this entry** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `Rack-Scale Computing.md`. - **HR-1149 — [[wiki/UALink|UALink]] `wiki_links_to` → this entry** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `UALink.md`.