# Google TPU The tensor processing unit was the first custom application-specific integrated circuit built for machine learning by a company that intended to run it in its own data centers. Its history is the clearest available case study in when custom silicon makes sense, and its influence on the field reaches further than its market share suggests. > [!note] The one-sentence version > A chip designed for one company's own workload, which turned out to be the workload everyone would have. ## The architectural approach The design commits to matrix multiplication in hardware: a large systolic array in which data flows through a grid of multiply-accumulate units, with weights held resident and activations streaming through, so that one data fetch feeds a great many operations. That structure is extremely efficient for the dense matrix work neural networks consist of, and correspondingly inflexible, which is the defining trade of a custom circuit; a function committed to silicon cannot be changed once etched, and in exchange it spends none of its transistors on generality. Contemporary alternatives from other operators take a different position within the same family, favoring many smaller flexible tensor engines over one large rigid grid, which is a genuine architectural disagreement rather than a marketing distinction. Deployment is at pod scale: many devices connected by a dedicated interconnect into a single training domain, with the same scale-up logic that governs the rest of this collection; see [[wiki/Scale-Up and Scale-Out|Scale-Up and Scale-Out]]. ## What the history shows The first generation was coined in 2015, and the architecture's development ran alongside the research that produced the transformer in 2017, a proximity that is itself instructive: hardware designed for a workload and research exploring that workload advanced together, and each shaped the other. The line has continued through many generations, the seventh being current as of October 2026, and a leading model developer has contracted for up to a million of these devices to train its models, which is among the largest custom-silicon commitments ever made. The economic lesson is the one the whole custom-silicon field rests on. Design costs run from tens to hundreds of millions of dollars before a part exists, which is recoverable only at very large internal volume; an operator serving its own workload at sufficient scale can justify it, and almost nobody else can. That is why custom accelerators are built by the largest operators and why merchant accelerators serve everyone else; see [[wiki/Accelerator|Accelerator]] and [[wiki/Hyperscaler|Hyperscaler]]. ## Relationships - **instance of:** [[wiki/Accelerator|Accelerator]] · [[wiki/Inference Accelerator|Inference Accelerator]] - **built by:** [[wiki/Hyperscaler|Hyperscaler]] · [[wiki/TSMC|TSMC]] - **depends on:** [[wiki/High-Bandwidth Memory|High-Bandwidth Memory]] · [[wiki/Advanced Packaging|Advanced Packaging]] - **organized by:** [[wiki/Scale-Up and Scale-Out|Scale-Up and Scale-Out]] - **part of:** [[wiki/Compute and Accelerator Systems|Compute and Accelerator Systems]] - **source articles:** [[articles/Vertically Integrating an AI Superpower from AI Factory to Citizen|Vertically Integrating an AI Superpower from AI Factory to Citizen]] · [[articles/The Gigawatt Is the New Measure of War|The Gigawatt Is the New Measure of War]] - **collection route:** [[collections/American Infrastructure|American Infrastructure]] · [[collections/American|American Collection]] ## Evidence posture - **Established:** the systolic matrix-array architecture and the flexibility-for-efficiency trade of custom circuits, which cannot be altered once etched; the first generation coined in 2015 as the first custom AI accelerator of its kind; the proximity of its development to the 2017 transformer architecture; pod-scale deployment over a dedicated interconnect; custom design costs from tens to hundreds of millions of dollars. - **Established (datestamped):** as of October 2026, the seventh generation is current, and a leading model developer has an agreement for up to one million of these devices for training. - **Established:** a contemporary operator-designed alternative favoring many smaller flexible tensor engines over one large matrix grid, with comparative performance positioning presented as that vendor's framing rather than as an independent result. ## Sources - [How Nvidia GPUs Compare To Google's And Amazon's AI Chips](https://www.cnbc.com/) — CNBC, October 2026; the 2015 origin, the transformer connection, the seventh generation, the million-device training agreement, the competing architectural framing, and custom design cost ranges.