# Infinity Fabric Infinity Fabric is a coherent interconnect used at three different scales by the same vendor: joining chiplets within a package, joining processor sockets within a server, and joining accelerators to each other and to their host. Its interest here is architectural rather than commercial; it is the clearest illustration of a single interconnect design reused from millimeters to meters, and of what coherence buys at each scale. > [!note] The one-sentence version > One interconnect architecture, stretched from between chiplets to across a rack, carrying coherent memory traffic at every scale. ## What coherence means and why it matters Several processors or accelerators may hold copies of the same memory location in their caches. **Cache coherence** is the guarantee that a write performed by one becomes visible to the others in a defined order, so that software can treat distributed memory as shared memory without explicit message passing. Maintaining it requires the interconnect to carry protocol traffic beyond the data itself: requests for ownership, invalidations, and responses. That overhead is why coherence is not applied everywhere; it is extremely convenient for the programmer and expensive to maintain as distance and participant count grow. The engineering judgement in every system is where to stop providing it. ## The three scales **Within the package.** Compute chiplets, input-output dies, and cache dies are joined by the fabric over the substrate or interposer, which is what allows a dozen pieces of silicon to present as one processor; see [[wiki/Chiplet|Chiplet]]. At this reach the links are short, wide, and cheap in power, so coherence is affordable and the programming model benefits enormously. **Between sockets.** Two processors in a server are joined coherently, so the operating system sees one memory space across both, with the understanding that memory attached to the other socket is slower to reach. This is the long-standing non-uniform memory access arrangement, and it is why performance-sensitive software pins work near its data. **Between accelerators, and from accelerator to host.** The fabric carries accelerator peer traffic within a tray and, in rack-scale designs, extends the coherent relationship between a processor and the accelerators it hosts, so host and accelerator address a shared space rather than copying across a bus. At rack scale the accelerator-to-accelerator role is served by the consortium scale-up fabric layered over Ethernet signaling, with standards-aligned Ethernet for scale-out; see [[wiki/UALink|UALink]], [[wiki/Ultra Ethernet|Ultra Ethernet]], and [[wiki/Scale-Up and Scale-Out|Scale-Up and Scale-Out]]. ## Why this architecture is instructive Reusing one interconnect across three scales is an economy of design: one protocol, one set of verification tools, one body of expertise, and a continuum rather than a set of translations between incompatible domains. It also makes the cost of distance legible. The same fabric is cheap between chiplets, acceptable between sockets, and expensive between racks, and the system's structure follows that gradient exactly. Every boundary in a modern machine, package, tray, rack, row, is a place where somebody decided the next increment of coherence was no longer worth its price, and reading a system's topology as a series of those decisions is the fastest way to understand why it is shaped as it is. ## Relationships - **joins:** [[wiki/Chiplet|Chiplet]] · [[wiki/Host CPU|Host CPU]] · [[wiki/Accelerator|Accelerator]] - **implements:** [[wiki/Scale-Up and Scale-Out|Scale-Up and Scale-Out]] at package and tray scale - **complemented at rack scale by:** [[wiki/UALink|UALink]] · [[wiki/Ultra Ethernet|Ultra Ethernet]] - **compared with:** [[wiki/NVLink|NVLink]] · [[wiki/PCIe|PCIe]] - **part of:** [[wiki/Compute and Accelerator Systems|Compute and Accelerator Systems]] - **source articles:** [[articles/Vertically Integrating an AI Superpower from AI Factory to Citizen|Vertically Integrating an AI Superpower from AI Factory to Citizen]] · [[articles/The Gigawatt Is the New Measure of War|The Gigawatt Is the New Measure of War]] - **collection route:** [[collections/American Infrastructure|American Infrastructure]] · [[collections/American|American Collection]] ## Evidence posture - **Established:** cache coherence semantics and the protocol overhead they require; the fabric's use within packages to join chiplets, between sockets for shared memory with non-uniform access, and for accelerator and host attachment; consortium scale-up fabric over Ethernet signaling with standards-aligned Ethernet for scale-out in current rack-scale designs. - **Strongly indicated:** design economy from reusing one interconnect architecture across scales; the vendor describes it and comparative engineering-cost data is not public. ## Sources - [Helios Is AMD's First AI System To Rival Nvidia Vera Rubin](https://www.cnbc.com/) — CNBC, October 2026; scale-up over the consortium fabric on Ethernet and consortium-aligned Ethernet scale-out. - Public vendor architecture documentation for coherent interconnect at package, socket, and accelerator scale, as of October 2026.