# NVIDIA B200 The B200 generation did two consequential things. It abandoned the single monolithic die, bonding two large compute dies at an ultra-tight interface and presenting them to software as one accelerator. And it added four-bit arithmetic support in hardware, which halved again the bytes required per value in the parts of a model that tolerate it. > [!note] The one-sentence version > Two dies acting as one, with arithmetic down to four bits, shipped in millions. ## Why two dies A single lithographic exposure cannot print a field larger than the reticle limit, and yield falls steeply with die area even below it; see [[wiki/Chiplet|Chiplet]]. Past a certain ambition, more silicon per accelerator requires more than one die. The approach taken here is the hybrid one: rather than many small chiplets, two large dies joined by a die-to-die interface fast enough that cache coherence and memory access cross it without software noticing. The package then carries both dies plus stacked memory on a shared substrate, which is an advanced packaging achievement before it is an architectural one; see [[wiki/Advanced Packaging|Advanced Packaging]]. ## Four-bit arithmetic Support for four-bit formats, with block scaling so that small groups of values share an exponent, is what allows current systems to quote peak figures at that precision. The gains are real and the verification obligation sits with the deployer, because degradation at four bits is uneven across task types; see [[wiki/Quantization|Quantization]]. ## Scale, and what it indicates More than six million accelerators of this family shipped over the preceding year, with rack-scale systems built from them leaving factories at a rate of roughly a thousand racks per week and a seventy-two-accelerator rack carrying a price on the order of three million dollars. Those are company figures and should be read as such, and they are indicative of something that matters: this is now volume manufacturing of a complex liquid-cooled integrated system, not a specialty product. The industrial achievement is the throughput as much as the architecture; see [[wiki/Rack and Cluster Integration|Rack and Cluster Integration]] and [[wiki/Industrial Competence|Industrial Competence]]. ## Relationships - **built from:** [[wiki/Chiplet|Chiplet]] · [[wiki/Advanced Packaging|Advanced Packaging]] · [[wiki/High-Bandwidth Memory|High-Bandwidth Memory]] - **mounted on:** [[wiki/NVIDIA HGX|NVIDIA HGX]] · [[wiki/NVIDIA NVL72|NVIDIA NVL72]] - **paired with:** [[wiki/NVIDIA Grace Blackwell|NVIDIA Grace Blackwell]] - **enables:** [[wiki/Quantization|Quantization]] at four-bit precision - **succeeded by:** [[wiki/NVIDIA B300|NVIDIA B300]] · [[wiki/NVIDIA Vera Rubin|NVIDIA Vera Rubin]] - **connected by:** [[wiki/NVLink|NVLink]] · [[wiki/NVSwitch|NVSwitch]] - **source articles:** [[articles/Vertically Integrating an AI Superpower from AI Factory to Citizen|Vertically Integrating an AI Superpower from AI Factory to Citizen]] · [[articles/The Gigawatt Is the New Measure of War|The Gigawatt Is the New Measure of War]] - **collection route:** [[collections/American Infrastructure|American Infrastructure]] · [[collections/American|American Collection]] ## Evidence posture - **Established:** two large compute dies bonded at a die-to-die interface and presented as one accelerator, packaged with stacked memory on a shared substrate; hardware support for four-bit formats with block scaling; the reticle field limit and defect-density yield relationship that motivate multi-die construction. - **Established:** published system building blocks pairing this part with dual forty-eight-core host processors and two terabytes of system memory. - **Established (datestamped), reported as company figures:** more than six million accelerators of this family shipped over the preceding year; rack-scale systems shipping at roughly one thousand racks per week; a seventy-two-accelerator rack priced on the order of three million dollars. - **Unresolved:** four-bit accuracy across task types, which requires task-specific evaluation rather than aggregate benchmarks. ## Sources - [How Nvidia GPUs Compare To Google's And Amazon's AI Chips](https://www.cnbc.com/) — CNBC, October 2026; shipment volume, rack shipping rate, rack price, and the seventy-two-accelerator rack acting as one accelerator. - Public accelerator architecture documentation, as of October 2026.