# NVIDIA CMX **Entity class:** Memory infrastructure **Integration priority:** P1 **Collections:** [[collections/Consciousness Continuity|Consciousness Continuity]] · [[collections/Neurotech|Neurotech]] · [[collections/Machine Succession|Machine Succession]] **Canonical source article:** [[articles/Mind Uploading and AI — The Host is Reusable and the Person is the Delta|Mind Uploading and AI — The Host is Reusable and the Person is the Delta]] ## Definition **NVIDIA CMX** — Pod-level context memory tier; link to Hot Interpreter/Cold Archive and KV Cache. ## Relationships <!-- BEGIN HUMANIZED RELATIONSHIPS 2026-09-11 --> This entry is routed through [[collections/Consciousness Continuity|Consciousness Continuity]], [[collections/Neurotech|Neurotech]], and [[collections/Machine Succession|Machine Succession]]. Its source context is developed in [[articles/2026 Annual Report on Brain-Computer Interfaces|2026 Annual Report on Brain-Computer Interfaces]], [[articles/Mind Uploading and AI — The Host is Reusable and the Person is the Delta|Mind Uploading and AI — The Host is Reusable and the Person is the Delta]], and [[articles/Technologies for Consciousness Mapping and Transfer|Technologies for Consciousness Mapping and Transfer]]. Status-qualified source edges are preserved in the terminal Research Edges section. ### Technology and research relationships - [[wiki/NVIDIA|NVIDIA]] develops **NVIDIA CMX**. Context memory storage platform. - **NVIDIA CMX** uses Spectrum-X Ethernet. Networking path for context tier. - The technical comparison identifies a convergence: **NVIDIA CMX** converges technically with [[wiki/Hot Interpreter and Cold Archive|Hot Interpreter and Cold Archive]]. Explicit hot HBM/DRAM vs shared flash context-memory hierarchy. - The technical comparison identifies a convergence: **NVIDIA CMX** converges technically with [[wiki/Memory Architecture|Memory Architecture]]. Infrastructure-level memory hierarchy. ### Key Relationships - **NVIDIA CMX** was powered by [[wiki/BlueField-4|BlueField-4]]. DPU/storage processor. - **NVIDIA CMX** is associated with GPU memory with pod-level context tier. Purpose-built context layer. - **NVIDIA CMX** is associated with [[wiki/KV Cache|KV cache]]. Shared context memory. - **NVIDIA CMX** provides petabyte-scale shared context capacity per GPU pod. NVIDIA technical description. <!-- END HUMANIZED RELATIONSHIPS 2026-09-11 --> ## Related Work in the Corpus <!-- BEGIN HUMANIZED CORPUS ROUTES 2026-09-11 --> - In [[articles/Mind Uploading and AI — The Host is Reusable and the Person is the Delta|Mind Uploading and AI — The Host is Reusable and the Person is the Delta]], **X. Memory became infrastructure** provides the narrative context for **NVIDIA CMX**: At CES in January 2026, NVIDIA announced the Inference Context Memory Storage Platform, powered by the BlueField-4 data processor and commercialized as NVIDIA CMX. - In [[articles/Mind Uploading and AI — The Host is Reusable and the Person is the Delta|Mind Uploading and AI — The Host is Reusable and the Person is the Delta]], **Host-infrastructure crosswalk** provides the narrative context for **NVIDIA CMX**: The active-state hierarchy is becoming infrastructure in its own right. <!-- END HUMANIZED CORPUS ROUTES 2026-09-11 --> ## Research Edges <!-- BEGIN HOST RESIDUAL RELATIONSHIP GRAPH 2026-09-10 --> #### Host–residual infrastructure patch — 2026-09-10 **Collections:** [[collections/Consciousness Continuity|Consciousness Continuity]] · [[collections/Neurotech|Neurotech]] · [[collections/Machine Succession|Machine Succession]] **Canonical source article:** [[articles/Mind Uploading and AI — The Host is Reusable and the Person is the Delta|Mind Uploading and AI — The Host is Reusable and the Person is the Delta]] **Related acquisition source:** [[articles/Technologies for Consciousness Mapping and Transfer|Technologies for Consciousness Mapping and Transfer]] **Relationship source:** [[research/Mind Uploading and AI Host-Residual Ecosystem Relationship Graph - 2026-09-10|Mind Uploading and AI Host-Residual Ecosystem Relationship Graph — 2026-09-10]] #### Host-infrastructure integration Pod-level context memory tier; link to Hot Interpreter/Cold Archive and KV Cache. #### Outgoing typed edges - **HR-0108 — `powered_by` → [[wiki/BlueField-4|BlueField-4]]** — **VERIFIED EXTERNAL**; evidence `WEB_NVIDIA_CMX`, `WEB_NVIDIA_CMX_NEWS`. DPU/storage processor. - **HR-0109 — `extends` → `GPU memory with pod-level context tier`** — **VERIFIED EXTERNAL**; evidence `WEB_NVIDIA_CMX`, `WEB_NVIDIA_CMX_TECH`. Purpose-built context layer. - **HR-0110 — `stores` → [[wiki/KV Cache|KV cache]]** — **VERIFIED EXTERNAL**; evidence `WEB_NVIDIA_CMX`, `WEB_NVIDIA_CMX_TECH`. Shared context memory. - **HR-0111 — `provides` → `petabyte-scale shared context capacity per GPU pod`** — **VERIFIED EXTERNAL**; evidence `WEB_NVIDIA_CMX_TECH`. NVIDIA technical description. - **HR-0112 — `uses` → `Spectrum-X Ethernet`** — **VERIFIED EXTERNAL**; evidence `WEB_NVIDIA_CMX`, `WEB_NVIDIA_CMX_NEWS`. Networking path for context tier. - **HR-0113 — `technical_convergence_with` → [[wiki/Hot Interpreter and Cold Archive|Hot Interpreter and Cold Archive]]** — **STRONG ANALYTIC CONVERGENCE**; evidence `WEB_NVIDIA_CMX_TECH`, `WIKI_ARCHIVE`. Explicit hot HBM/DRAM vs shared flash context-memory hierarchy. - **HR-0114 — `technical_convergence_with` → [[wiki/Memory Architecture|Memory Architecture]]** — **ANALYTIC CONVERGENCE**; evidence `WEB_NVIDIA_CMX`, `WIKI_ARCHIVE`. Infrastructure-level memory hierarchy. #### Incoming typed edges - **HR-0107 — [[wiki/NVIDIA|NVIDIA]] `develops` → this entry** — **VERIFIED EXTERNAL**; evidence `WEB_NVIDIA_CMX`, `WEB_NVIDIA_CMX_TECH`. Context memory storage platform. <!-- END HOST RESIDUAL RELATIONSHIP GRAPH 2026-09-10 -->