# NVIDIA HGX HGX is a baseboard specification: eight accelerators mounted on one board, wired together by the vendor's scale-up fabric, with standardized mechanical, electrical, and thermal interfaces to whatever chassis a system builder puts around it. It became the unit in which data-center accelerators are bought, and that standardization did more for deployment volume than any single chip generation. > [!note] The one-sentence version > Eight accelerators pre-wired on one board, so a server builder designs a chassis rather than an interconnect. ## Why it exists Early multi-accelerator servers were bespoke. Each builder worked out its own board layout, its own peer-to-peer topology, its own power delivery, and its own thermal solution, which meant every system was a separate engineering project and no two performed alike. Standardizing the baseboard moved all of that difficulty into one component designed once by the party that understood the fabric best. A builder then supplies the chassis, the hosts, the power, the cooling, the storage, and the network, and the accelerator complex arrives as a known quantity. The mounting standard beneath it, a socketed module format rather than a card in an expansion slot, is what allows higher power delivery and direct fabric wiring between neighbors; a card in a slot is limited by the slot's power and by routing through the host bus. See [[wiki/PCIe|PCIe]] and [[wiki/OCP Accelerator Module|OCP Accelerator Module]] for the open counterpart of the same idea. ## What a system around it contains Two host processors, two to three terabytes of system memory, local flash for boot and data, ordinary bonded host networking, and much higher-rate interfaces for the accelerator cluster fabric; see [[wiki/Host CPU|Host CPU]] and [[wiki/Compute and Accelerator Systems|Compute and Accelerator Systems]]. Inside the baseboard, switch silicon converts the eight accelerators into an all-to-all domain so every pair communicates at full bandwidth; see [[wiki/NVLink|NVLink]] and [[wiki/NVSwitch|NVSwitch]]. The resulting eight-accelerator domain was the industry's scale-up unit for several generations, and it remains the volume configuration. Rack-scale systems extended the same logic to seventy-two accelerators, which is a different integration level rather than a larger server; see [[wiki/Rack-Scale Computing|Rack-Scale Computing]] and [[wiki/Scale-Up and Scale-Out|Scale-Up and Scale-Out]]. ## Generations The baseboard has carried successive accelerator families with the same external contract: [[wiki/NVIDIA H100|H100]], [[wiki/NVIDIA H200|H200]], [[wiki/NVIDIA B200|B200]], and [[wiki/NVIDIA B300|B300]], each raising per-accelerator memory, bandwidth, and arithmetic while preserving the eight-module arrangement. That continuity is the point: an operator's chassis, power, and cooling investments survive an accelerator generation, which is what makes a refresh a procurement rather than a rebuild. ## Relationships - **carries:** [[wiki/NVIDIA H100|NVIDIA H100]] · [[wiki/NVIDIA H200|NVIDIA H200]] · [[wiki/NVIDIA B200|NVIDIA B200]] · [[wiki/NVIDIA B300|NVIDIA B300]] - **interconnected by:** [[wiki/NVLink|NVLink]] · [[wiki/NVSwitch|NVSwitch]] - **hosted by:** [[wiki/Host CPU|Host CPU]] · [[wiki/Server OEM and System Integration|Server OEM and System Integration]] - **compared with:** [[wiki/OCP Accelerator Module|OCP Accelerator Module]] · [[wiki/AMD Instinct GPUs|AMD Instinct]] - **part of:** [[wiki/Compute and Accelerator Systems|Compute and Accelerator Systems]] · [[wiki/AI Stack|AI Stack]] - **source articles:** [[articles/Vertically Integrating an AI Superpower from AI Factory to Citizen|Vertically Integrating an AI Superpower from AI Factory to Citizen]] · [[articles/The Gigawatt Is the New Measure of War|The Gigawatt Is the New Measure of War]] - **collection route:** [[collections/American Infrastructure|American Infrastructure]] · [[collections/American|American Collection]] ## Evidence posture - **Established:** the eight-module baseboard specification with standardized mechanical, electrical, and thermal interfaces; socketed module mounting permitting higher power delivery and direct peer wiring than expansion-slot cards; in-baseboard switch silicon producing an all-to-all eight-accelerator domain; successive accelerator families carried on the same external contract. - **Established:** published system building blocks pairing the baseboard with dual host processors, two to three terabytes of system memory, local boot and data flash, bonded host networking, and higher-rate cluster fabric interfaces. - **Strongly indicated:** baseboard standardization contributing more to deployment volume than any single chip generation; the structural reasoning is clear and comparative attribution is not published. ## Sources - Public accelerator baseboard and server platform documentation, as of October 2026.