# NVLink NVLink is a dedicated interconnect that lets one accelerator read and write another's memory directly, without passing through the host processor or the expansion bus. Inside a modern system it replaces the general-purpose bus for accelerator-to-accelerator traffic, and with switch silicon it binds dozens of accelerators into one pool of memory that a training program can address as a single very large device. > [!note] The one-sentence version > A private mesh that turns many accelerators into one, by letting each one treat the others' memory as its own. ## Why it exists Tensor-parallel training generates sustained exchange between accelerators measured in hundreds of gigabytes per second. Routing that through the host over [[wiki/PCIe|PCIe]] is the lesson every early multi-accelerator system taught: a bus built for reaching devices through a shared hierarchy, with the host in the address path, is both too slow and too contended. The insight behind the answer is worth keeping, because it generalizes: a gradient synchronization or an activation hand-off is memory traffic, and memory wants a memory fabric, with direct loads and stores rather than messages staged through a third party's address space. ## Prerequisites - **Link:** a bundle of differential lanes; each generation raises the per-lane rate, and each accelerator carries many links whose sum is the figure that matters for system design. - **Peer-to-peer access:** one accelerator executing a read or write directly into another's memory, so that a tensor shard on a neighboring device is addressable memory rather than a message to be sent. - **Scale-up domain:** the set of accelerators reachable at full fabric speed; see [[wiki/Scale-Up and Scale-Out|Scale-Up and Scale-Out]]. - **Collective library:** the software that implements group operations such as all-reduce over whatever fabric is present; see [[wiki/Collective Communication|Collective Communication]]. ## How it works Accelerators on a board or tray are cabled together and firmware enumerates reachability. Through the programming model a kernel on one device receives addresses that resolve into another device's memory; the hardware routes the request across the fabric rather than to the host. Loads and stores issued by the executing code cross the link and the remote memory answers, so the latency floor is memory access plus fabric traversal, with no host processor, network interface, or kernel queue in the path. Direct meshes are limited by how many neighbors each device can wire to. Inserting switch silicon collapses that limitation: every device's links land on switches, and every device gains equal full-bandwidth reach to every other in the domain; see [[wiki/NVSwitch|NVSwitch]]. That step is the pivotal one, because a point-to-point mesh becomes a non-blocking fabric in which every pair is equidistant, and collective libraries can plan routes accordingly. Switch trays then became a rack form factor, producing seventy-two-accelerator all-fabric domains in which the rack is the computer and rows of racks are connected by the scale-out network. ## Position and alternatives - **Upstream:** accelerator silicon generations and the rack engineering around them; see [[wiki/Rack and Cluster Integration|Rack and Cluster Integration]]. - **Downstream:** collective libraries and every tensor-parallel training framework running on this hardware. - **Alternatives:** a competing vendor's coherent interconnect performs the same role within its own platforms, and the open consortium answer standardizes the same memory-semantic claim across vendors; see [[wiki/Infinity Fabric|Infinity Fabric]] and [[wiki/UALink|UALink]]. - **Degraded case:** large tensor-parallel widths become uneconomic, accelerators revert to host-mediated exchange, and training efficiency at scale falls sharply. ## Lineage and trajectory The first generation arrived in 2016 with accelerator-native peer links; subsequent generations widened the mesh; switch silicon turned meshes into all-to-all domains; a later generation made the eight-accelerator baseboard the uniform baseline; and the current generation carries seventy-two-accelerator rack domains. Each step pushed the same boundary outward: how many accelerators can share memory at full speed. The live question is whether that semantic becomes an open standard, which is precisely the bet the consortium alternative represents, and buyers' appetite for the capability without single-vendor supply is what will settle it. ## Relationships - **implements:** [[wiki/Scale-Up and Scale-Out|Scale-Up and Scale-Out]] - **switched by:** [[wiki/NVSwitch|NVSwitch]] - **replaces for peer traffic:** [[wiki/PCIe|PCIe]] - **used by:** [[wiki/Collective Communication|Collective Communication]] · [[wiki/CUDA|CUDA]] - **competes with:** [[wiki/Infinity Fabric|Infinity Fabric]] · [[wiki/UALink|UALink]] - **part of:** [[wiki/Rack-Scale Computing|Rack-Scale Computing]] · [[wiki/Compute and Accelerator Systems|Compute and Accelerator Systems]] - **source articles:** [[articles/Vertically Integrating an AI Superpower from AI Factory to Citizen|Vertically Integrating an AI Superpower from AI Factory to Citizen]] · [[articles/The Gigawatt Is the New Measure of War|The Gigawatt Is the New Measure of War]] - **collection route:** [[collections/American Infrastructure|American Infrastructure]] · [[collections/American|American Collection]] ## Evidence posture - **Established:** direct accelerator-to-accelerator memory semantics bypassing the host; per-generation increases in per-link rate and per-accelerator aggregate bandwidth; switch silicon converting meshes to all-to-all domains; eight-accelerator baseboards as a uniform baseline and seventy-two-accelerator rack domains as shipping configurations; the first generation dating to 2016. - **Established:** the insufficiency of the general expansion bus for sustained peer training traffic. - **Unresolved:** whether open cross-vendor scale-up fabrics displace proprietary ones; the deciding evidence is shipped volume and measured efficiency of consortium-based systems. ## Sources - Public vendor documentation for accelerator interconnect generations and rack-scale configurations, as of October 2026. - [Helios Is AMD's First AI System To Rival Nvidia Vera Rubin](https://www.cnbc.com/) — CNBC, October 2026; the competing rack-scale architecture and its consortium-based scale-up fabric.