# NVSwitch A switch for an accelerator fabric is a crossbar for memory operations. Each accelerator's links terminate on switch silicon rather than on neighboring accelerators, and the switch forwards reads and writes so that every device reaches every other at full bandwidth. The change from mesh to switch is what made large scale-up domains possible, and it is a textbook case of a topology problem solved by adding a dedicated element. > [!note] The one-sentence version > Wire every accelerator to a switch instead of to its neighbors, and every accelerator becomes an equal neighbor of every other. ## Why it exists: the radix problem Each accelerator has a finite number of links. In a direct mesh those links must be divided among peers, so a group of eight devices wired directly to one another spends most of its links on connectivity and leaves little bandwidth per pair; and the geometry is uneven, since some pairs are adjacent and others require a hop through a third device. Uneven topology is poison for collective operations, because a group operation runs at the speed of its slowest pair, and software must then be written to the particular shape of the wiring. A switch resolves both at once. Devices spend all their links on reaching the switch; the switch provides the connectivity. Every pair becomes equidistant at full bandwidth, and the collective library can plan routes knowing the fabric is uniform; see [[wiki/Collective Communication|Collective Communication]]. Uniformity is worth more than raw link count, because uniformity is what software can rely on. ## What it actually is Switch silicon for a memory fabric is not a packet forwarder in the ordinary networking sense. It is a non-blocking crossbar carrying memory semantics, with the addressing, ordering, and error behavior that loads and stores require, built to a latency budget measured in tens of nanoseconds rather than microseconds. Modern generations also perform reductions inside the switch, so that a sum across many devices is computed as data passes through rather than being gathered to one device first; moving arithmetic into the network is one of the more elegant optimizations in the whole stack, and it reduces both traffic and latency for the most common collective. Physically the switches occupy their own trays in a rack-scale system; a current design uses six switch trays alongside eighteen compute trays. Links inside the rack are short enough for copper, which is cheaper and lower-power than optics at that reach; see [[wiki/Data Center Optics|Data Center Optics]]. ## Position - **Upstream:** the accelerator fabric generation and the rack mechanical design. - **Downstream:** the scale-up domain size, and therefore the tensor-parallel width available to training software; see [[wiki/Scale-Up and Scale-Out|Scale-Up and Scale-Out]]. - **Alternatives:** a direct mesh, which works at small scale and does not reach past a few devices efficiently; and switched implementations of the open consortium fabrics, which aim at the same function across vendors; see [[wiki/UALink|UALink]]. - **Degraded case:** the scale-up domain shrinks to what a mesh supports, and every layer above must be rewritten for a smaller, uneven fabric. ## Relationships - **switches:** [[wiki/NVLink|NVLink]] - **enables:** [[wiki/Scale-Up and Scale-Out|Scale-Up and Scale-Out]] · [[wiki/Rack-Scale Computing|Rack-Scale Computing]] - **accelerates:** [[wiki/Collective Communication|Collective Communication]] - **installed as:** [[wiki/Compute Tray|Compute Tray]] peers in [[wiki/Data Center Rack|Data Center Rack]] - **compared with:** [[wiki/UALink|UALink]] · [[wiki/Infinity Fabric|Infinity Fabric]] - **source articles:** [[articles/Vertically Integrating an AI Superpower from AI Factory to Citizen|Vertically Integrating an AI Superpower from AI Factory to Citizen]] · [[articles/The Gigawatt Is the New Measure of War|The Gigawatt Is the New Measure of War]] - **collection route:** [[collections/American Infrastructure|American Infrastructure]] · [[collections/American|American Collection]] ## Evidence posture - **Established:** the radix limitation of direct meshes and the uneven pair bandwidth it produces; switch silicon providing equidistant full-bandwidth reachability; non-blocking crossbar operation carrying memory semantics at nanosecond-class latency; in-network reduction of collective operations; switch trays as a distinct rack element, with a current design using six switch trays alongside eighteen compute trays; copper's suitability at in-rack reach. - **Strongly indicated:** in-network reduction materially improving all-reduce performance at scale; vendor measurements agree in direction and independent cross-platform data is limited. ## Sources - [Helios Is AMD's First AI System To Rival Nvidia Vera Rubin](https://www.cnbc.com/) — CNBC, October 2026; six switches alongside eighteen compute trays in a current rack-scale system. - Public vendor documentation for accelerator fabric switch silicon, as of October 2026.