# NorthPole **Entity class:** Concept or analytic term **Type:** AI accelerator architecture **Collection:** [[collections/Neurotech|Neurotech]] **Primary source:** [[articles/2026 Annual Report on Brain-Computer Interfaces|2026 Annual Report on Brain-Computer Interfaces]] ## Definition NorthPole is IBM's memory-compute-integrated accelerator architecture discussed as a low-latency, high-bandwidth inference system. ## Relationships [[wiki/NorthPole|NorthPole]] is related to [[wiki/IBM|IBM]], [[wiki/Neuromorphic Computing|neuromorphic computing]], and near-body neural inference as a comparative architecture. <!-- BEGIN HUMANIZED RELATIONSHIPS 2026-09-11 --> This entry's documented connections are expressed in its definition and related-work routes, with provenance retained in the source-linked material. <!-- END HUMANIZED RELATIONSHIPS 2026-09-11 --> ## Source route [[articles/2026 Annual Report on Brain-Computer Interfaces|2026 Annual Report on Brain-Computer Interfaces]] · [[collections/Neurotech|Neurotech]] ## Neurotech source route **Collection:** [[collections/Neurotech|Neurotech]] **Source article:** [[articles/The Organic-Synthetic Brain Atlas|The Organic-Synthetic Brain Atlas]] ## Related Work in the Corpus <!-- BEGIN HUMANIZED CORPUS ROUTES 2026-09-11 --> - In [[articles/The Organic-Synthetic Brain Atlas|The Organic-Synthetic Brain Atlas]], **IV.3 — IBM TrueNorth and NorthPole: From Spiking to Inference Acceleration** provides the narrative context for **NorthPole**: The successor architecture, NorthPole, presented at Hot Chips 2023 and detailed in Science in October 2023, represents a deliberate departure from pure spiking neural network execution toward optimized neural network inference… - In [[articles/2026 Annual Report on Brain-Computer Interfaces|2026 Annual Report on Brain-Computer Interfaces]], **Neuromorphic Hardware: Collapsing the Cloud Dependency Objection** provides the narrative context for **NorthPole**: IBM's NorthPole, scaled to a 288-card system by November 2025, achieves 115 peta-ops for LLM inference at 4-bit precision with 3.7 PB/s bandwidth consuming ~30kW—demonstrating cognitive-task-optimized architectures can approach… <!-- END HUMANIZED CORPUS ROUTES 2026-09-11 --> ## Research Inferences <!-- BEGIN RESEARCH INFERENCES 2026-09-11 --> These entries translate the forward-looking register in [[research/Research Inferences|Research Inferences]] into ordinary wiki prose. The tier labels apply to the inference, not automatically to every factual anchor inside it. The interpretive frame comes from [[articles/Technologies for Consciousness Mapping and Transfer|Technologies for Consciousness Mapping and Transfer]] and [[articles/Mind Uploading and AI — The Host is Reusable and the Person is the Delta|Mind Uploading and AI — The Host is Reusable and the Person is the Delta]]. Collection route: [[collections/Neurotech|Neurotech]]. - **INF-0177 — Established.** NorthPole's co-location of memory with compute addresses the von Neumann bottleneck directly, which is the same architectural insight biology implements with synapses. Convergent architecture between silicon and tissue is what makes cross-substrate portability of neural workloads conceivable. <!-- END RESEARCH INFERENCES 2026-09-11 -->