# Silicon Wafer Every processor, memory die, network controller, and power device in this collection begins as part of a single polished disc of silicon. It looks like nothing: a grey mirror the width of a dinner plate. Producing one to the required standard was for decades among the most demanding industrial tasks on Earth, and the wafer sets the geometric and economic floor beneath all chipmaking. Understanding it explains why chips arrive in batches, why their diameter stopped growing, and why a wafer shortage cannot be engineered around. > [!note] The one-sentence version > A wafer is a 300 mm disc of the purest material humans manufacture, flat to atomic tolerance, onto which dozens to hundreds of chips are printed at once and then cut apart. ## Why it exists Chips are made by repetition: deposit, print, etch, implant, measure, repeat. That sequence needs a substrate that is rigid, flat, chemically uniform, and large enough to carry many devices through the line together, so that the cost of each pass is shared across everything on the disc. It also needs a continuous crystal. Transistor behavior depends on an unbroken lattice with a known orientation, because a discontinuity scatters the electrons the device is built to control. A slice of one grown crystal supplies both properties at once. ## Prerequisites - **Purity:** electronic-grade silicon is refined past nine nines; metallic contamination measured in parts per billion is enough to ruin devices. - **Single crystal:** one continuous lattice throughout, as distinct from glassy or many-grained material. - **Flatness:** photolithography projects an image with a shallow depth of focus, so the surface must be flat at the atomic scale across the whole disc; see [[wiki/Semiconductor Lithography|Semiconductor Lithography]]. - **Die:** one finished chip as produced on the wafer, before the wafer is cut. - **Yield:** the share of dies on a wafer that work. Because defects land at random, yield falls as die area grows; this single relationship drives the move to [[wiki/Chiplet|chiplets]]. ## How a wafer is made 1. **Refine.** Quartz is reduced to metallurgical silicon, converted to a volatile compound, distilled, and deposited back as high-purity polysilicon feedstock. 2. **Grow.** In the Czochralski method, polysilicon is melted in a crucible, a seed crystal is touched to the surface, and the seed is rotated and drawn slowly upward. Silicon solidifies onto it in the seed's orientation, producing a cylindrical ingot weighing hundreds of kilograms. Pull rate and thermal control govern the lattice perfection of everything cut from it. 3. **Slice.** A wire saw carrying thousands of diamond-charged wires under tension cuts the ingot into rough discs under a millimeter thick. 4. **Shape and etch.** Lapping and grinding bring diameter and thickness into specification; chemical etching removes saw marks and the lattice damage beneath them. 5. **Polish.** Chemical-mechanical planarization brings the surface to atomic flatness, producing one of the flattest surfaces made at industrial scale. 6. **Clean and inspect.** Ultra-pure wet cleaning and defect metrology verify the disc before it is sealed for transport. ## Classes of wafer - **Prime:** the highest crystalline and cleanliness grade, used for production devices. - **Test or monitor:** lower-grade discs used to qualify a process line without consuming prime material. - **Epitaxial:** a prime wafer overgrown with an additional crystal-perfect layer tuned for a particular device. - **Silicon-on-insulator:** device silicon above an insulating layer, valuable in radio-frequency and low-power work. - **Reclaim:** previously used discs refinished for process monitoring. ## Diameter, and why 300 mm held Larger discs amortize edge losses and fixed per-pass costs across more dies; 200 mm gave way to 300 mm around the turn of the century, which raised usable area by roughly a factor of 2.3 and raised the chips per pass with it. A 450 mm generation was projected repeatedly and deferred each time, because it would require an entire new generation of tooling, handling, and metrology whose cost the industry has never chosen to carry. Analog and foundational devices still run profitably on 200 mm lines, often on equipment handed down from leading-edge fabs; that second-hand economy is why a component costing cents can be made in a factory that once printed processors. ## Stack position - **Upstream:** polysilicon refining, crucible and consumable supply, wire saws, polishing slurries, and metrology. - **Downstream:** every fab, and therefore every device in the stack. - **Function and vendor:** silicon's role in logic and memory at scale is presently without substitute; gallium arsenide, silicon carbide, and gallium nitride serve power and radio-frequency niches where their properties win. - **Degraded case:** fabs idle. Wafer supply is the one input for which no amount of capital upstream or software above provides relief. ## Lineage and trajectory Wafer making has advanced quietly and continuously: flatter surfaces, controlled oxygen content, fewer particles, better lattice engineering for power devices. It advanced so well that the binding constraint on logic scaling moved on to transistors, then to packaging, then to memory. The present movement is geographic: 300 mm prime capacity, long concentrated in a few countries, is being rebuilt in more of them under national semiconductor programs. Everything above the wafer rests on an industrial base built across decades, whose cost per square centimeter anchors the economics of all computing. ## Relationships - **substrate for:** [[wiki/Semiconductor Lithography|Semiconductor Lithography]] · [[wiki/Transistor|Transistor]] · [[wiki/Foundry|Foundry]] - **cut into:** [[wiki/Chiplet|Chiplet]] - **part of:** [[wiki/Upstream Industrial Foundation|Upstream Industrial Foundation]] - **supply risk recorded in:** [[wiki/Supply Chain Chokepoint|Supply Chain Chokepoint]] - **source articles:** [[articles/Vertically Integrating an AI Superpower from AI Factory to Citizen|Vertically Integrating an AI Superpower from AI Factory to Citizen]] · [[articles/The Gigawatt Is the New Measure of War|The Gigawatt Is the New Measure of War]] - **collection route:** [[collections/American Infrastructure|American Infrastructure]] · [[collections/American|American Collection]] ## Evidence posture - **Established:** the Czochralski growth, slicing, and polishing sequence; nine-nines-class purity; atomic-scale flatness requirement; 300 mm as the current standard and the repeated deferral of 450 mm; the roughly 2.3-times area gain from 200 mm to 300 mm. - **Established:** hand-me-down 200 mm equipment economics in analog and foundational device manufacture. - **Strongly indicated:** regionalization of prime wafer capacity under national incentive programs; announced investments are documented, and the resulting capacity shares are still accruing. ## Sources - [How AI Is Pushing the Semiconductor Supply Chain to the Limit](https://www.bloomberg.com/) — Bloomberg Originals, October 2026; wafer economics, 200 mm against 300 mm area, dies per wafer, equipment hand-me-down economics. - Industry engineering literature on crystal growth and wafer finishing, as of October 2026.