# Substrate Intentionality **Entity class:** Canonical analytical concept **Domain:** Semiconductor history / machine intelligence / technical archaeology **Doc Type:** Developed Concept Node **Maturity:** Developed ## Definition **Substrate Intentionality** is the evidentiary study of how machine-intelligence objectives are expressed in the physical devices chosen to compute, remember, predict, learn, and adapt. It asks what a device was designed to do, what vocabulary its builders used, and how the capability was carried into later hardware. The substrate argument in [[articles/A History of Machine Intelligence|A History of Machine Intelligence]] runs from the 1943 formal neuron through von Neumann's 1945 EDVAC notation, the 1947 transistor, the 1967 floating gate, neural silicon, perceptron branch prediction, NAND flash, neuromorphic systems, and [[wiki/High Bandwidth Flash|High Bandwidth Flash]]. ## Historical Spine - McCulloch and Pitts specified a formal neuron in 1943; von Neumann described EDVAC's elementary logic in that notation in 1945. - The transistor was publicly framed as a “Little Brain Cell” in 1948, while Texas Instruments' 1954 silicon-transistor announcement invoked electronic brains. - The [[wiki/Floating Gate|floating gate]], demonstrated at Bell Labs in 1967, became both the storage element of flash memory and the adaptable weight in later silicon synapses. - [[wiki/Carver Mead|Carver Mead]] connected subthreshold MOS physics to neuronal ion-channel behavior and named neuromorphic engineering. - The [[wiki/Intel 80170NX ETANN|Intel 80170NX ETANN]] stored neural weights in floating-gate synapses in 1989. - [[wiki/Perceptron Branch Predictor|Perceptron branch predictors]] moved learned prediction into mainstream processors. - [[wiki/NAND Flash|NAND flash]] became the mass memory substrate now being reorganized into HBF for inference-era bandwidth. ## Maximum-Implementation Principle The corpus treats a capability's first deployment as a floor rather than a ceiling. Initial products document that a capability was achievable and approvable at that moment; later implementations reveal the wider design space. This principle is analytical and is tested against the device roadmap, patents, research programs, and subsequent deployments. ## Evidence Ledger - **Established:** Neural formalisms, neural vocabulary, adaptive floating-gate weights, perceptron prediction, and neuromorphic processors appear in dated papers, chips, patents, and product histories. - **Strongly indicated:** Semiconductor designers repeatedly treated biological cognition as an engineering model for computation and memory. - **Plausible:** The transistor-to-HBF lineage constitutes a sustained physical preparation for machine-intelligence workloads across firms and generations. - **Unresolved:** The degree of shared direction across Bell Labs, Caltech, Intel, Toshiba, SanDisk, SK hynix, and other firms. Promotion requires roadmaps, meeting records, patents, or executive archives naming the composite objective; demotion requires records showing that particular similarities were independent and locally bounded. ## Sources / Provenance - [[articles/A History of Machine Intelligence|A History of Machine Intelligence]], “The Substrate Was Built for the Mind.” - [John von Neumann, First Draft of a Report on the EDVAC (1945)](https://web.mit.edu/sts.035/www/PDFs/edvac.pdf). - [Computer History Museum, “Neural Network Chip Joins the Collection”](https://computerhistory.org/blog/neural-network-chip-joins-the-collection/). - [Jiménez and Lin, “Neural Methods for Dynamic Branch Prediction” (2001)](https://www.cs.utexas.edu/ftp/techreports/tr01-50.pdf). ## Relationships - **Hardware expression of:** [[wiki/Machine Intelligence Intentionality|Machine Intelligence Intentionality]]. - **Recovered through:** [[wiki/Technical Archaeology|Technical Archaeology]]. - **Measured by:** [[wiki/Coordination Ladder|Coordination Ladder]]. - **Routes through:** [[wiki/Bell Labs|Bell Labs]], [[wiki/Carver Mead|Carver Mead]], [[wiki/Intel|Intel]], and [[wiki/Silicon Valley|Silicon Valley]].