UALink - Bryant McGill

# UALink **Entity class:** Concept or analytic term **Domain:** Accelerator Interconnect / Open Standards **Doc Type:** Technical Standard Node **Maturity:** Emerging ## Definition **UALink**, Ultra Accelerator Link, is an open scale-up interconnect architecture for low-latency, high-bandwidth communication among accelerators and switches inside AI computing pods. ## Governing Boundary UALink standardizes accelerator-to-accelerator communication and associated system management rather than ordinary data-center scale-out traffic. Its load, store and atomic semantics are intended to let many accelerators participate in a larger coordinated compute and memory domain. ## Higher-Order Capability The standard changes the unit of computation. A collection of heterogeneous accelerator components can be designed around a shared scale-up fabric rather than one vendor's proprietary internal link. The organizational gain is an open boundary around the accelerator pod. ## Relation to Governance Interconnect standards allocate architectural power. They decide which devices can become peers, how the fabric is managed and where vendor differentiation remains possible. In [[wiki/Rack-Scale Computing|Rack-Scale Computing]], that decision shapes locality, fault domains and workload placement. ## Failure Modes Specification availability does not guarantee mature multi-vendor products or operational portability. Management, topology, software support and conformance are as important as link semantics. ## Related Ontology [[wiki/Standards as Governance|Standards as Governance]] · [[wiki/Rack-Scale Computing|Rack-Scale Computing]] · [[wiki/CXL|CXL]] · [[wiki/Ultra Ethernet|Ultra Ethernet]] · [[wiki/Optical Fabric|Optical Fabric]] ## Sources / Provenance - [UALink Consortium — About UALink](https://ualinkconsortium.org/about-ualink/) - [UALink Consortium — Specifications](https://ualinkconsortium.org/specification/) ## Relationships  This entry is routed through [[collections/Consciousness Continuity|Consciousness Continuity]], [[collections/Neurotech|Neurotech]], and [[collections/Machine Succession|Machine Succession]]. Its source context is developed in [[articles/Mind Uploading and AI — The Host is Reusable and the Person is the Delta|Mind Uploading and AI — The Host is Reusable and the Person is the Delta]] and [[articles/Technologies for Consciousness Mapping and Transfer|Technologies for Consciousness Mapping and Transfer]]. Status-qualified source edges are preserved in the terminal Research Edges section. ### Key Relationships - **UALink** is associated with 1,024 accelerators per AI pod. Current 200G 1.0. ### Technology and research relationships - **UALink** supports 200G per lane. Current spec. ### Connections in this corpus - **UALink** is connected in the corpus with [[wiki/Standards as Governance|Standards as Governance]]. Open scale-up interconnect defines who can participate in shared accelerator domains.  ## Read First in the Wiki  - [[wiki/AI Factory|AI Factory]] — supplies the related concept or analytic term context needed to place **UALink** within the wider system. - [[wiki/CXL|CXL]] — supplies the related concept or analytic term context needed to place **UALink** within the wider system. - [[wiki/Optical Fabric|Optical Fabric]] — supplies the related concept or analytic term context needed to place **UALink** within the wider system. - [[wiki/Rack-Scale Computing|Rack-Scale Computing]] — supplies the related concept or analytic term context needed to place **UALink** within the wider system. - [[wiki/Standards as Governance|Standards as Governance]] — supplies the related technical standard or protocol context needed to place **UALink** within the wider system. - [[wiki/Ultra Ethernet|Ultra Ethernet]] — supplies the related concept or analytic term context needed to place **UALink** within the wider system.  ## Related Work in the Corpus  - In [[articles/Mind Uploading and AI — The Host is Reusable and the Person is the Delta|Mind Uploading and AI — The Host is Reusable and the Person is the Delta]], **Host-infrastructure crosswalk** provides the narrative context for **UALink**: Finally, UALink, the Ultra Ethernet Consortium, DMTF Redfish, CXL, 800 VDC AI data-center power, Maia 200, BlueField-4, and BlueField-4 STX expose the receiving substrate as an interoperable stack of fabrics, management planes,…  ## Research Edges  #### Host–residual infrastructure patch — 2026-09-10 **Resolved aliases:** `UALink Common 2.0`, `UALink Manageability 1.0`, `UALink Consortium board ecosystem`, `UALink Consortium` **Collections:** [[collections/Consciousness Continuity|Consciousness Continuity]] · [[collections/Neurotech|Neurotech]] · [[collections/Machine Succession|Machine Succession]] **Canonical source article:** [[articles/Mind Uploading and AI — The Host is Reusable and the Person is the Delta|Mind Uploading and AI — The Host is Reusable and the Person is the Delta]] **Related acquisition source:** [[articles/Technologies for Consciousness Mapping and Transfer|Technologies for Consciousness Mapping and Transfer]] **Relationship source:** [[research/Mind Uploading and AI Host-Residual Ecosystem Relationship Graph - 2026-09-10|Mind Uploading and AI Host-Residual Ecosystem Relationship Graph — 2026-09-10]] #### Host-infrastructure integration This entry is expanded through the concrete host-side relationships and status-qualified edges below. #### Outgoing typed edges - **HR-0177 — `connects_up_to` → `1,024 accelerators per AI pod`** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK`. Current 200G 1.0. - **HR-0178 — `supports` → `200G per lane`** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK`. Current spec. - **HR-0179 — `adds` → `in-network compute`** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK`. Current spec family. - **HR-0180 — `uses` → `gNMI`** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK`. Management API. - **HR-0181 — `uses` → `YANG`** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK`. Management model. - **HR-0182 — `uses` → `SAI`** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK`. Management API/model. - **HR-0183 — `uses` → [[wiki/DMTF Redfish|Redfish]]** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK`. Cross-standard management. - **HR-1149 — `wiki_links_to` → [[wiki/CXL|CXL]]** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `UALink.md`. - **HR-1150 — `wiki_links_to` → [[wiki/Optical Fabric|Optical Fabric]]** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `UALink.md`. - **HR-1151 — `wiki_links_to` → [[wiki/Rack-Scale Computing|Rack-Scale Computing]]** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `UALink.md`. - **HR-1152 — `wiki_links_to` → [[wiki/Standards as Governance|Standards as Governance]]** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `UALink.md`. - **HR-1153 — `wiki_links_to` → [[wiki/Ultra Ethernet|Ultra Ethernet]]** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `UALink.md`. - **HR-1388 — `cross_threads` → [[wiki/Standards as Governance|Standards as Governance]]** — **HIGH VALUE CROSS THREAD**; evidence `ARTICLE`, `WIKI_ARCHIVE`. Open scale-up interconnect defines who can participate in shared accelerator domains. - **HR-1586 — `includes` → [[wiki/Alibaba|Alibaba]]** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK_MEMBERS`. Board member. - **HR-1587 — `includes` → [[wiki/AMD|AMD]]** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK_MEMBERS`. Board member. - **HR-1588 — `includes` → [[wiki/Apple|Apple]]** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK_MEMBERS`. Board member. - **HR-1589 — `includes` → [[wiki/Amazon Web Services|AWS]]** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK_MEMBERS`. Board member. - **HR-1590 — `includes` → [[wiki/Cisco|Cisco]]** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK_MEMBERS`. Board member. - **HR-1591 — `includes` → [[wiki/Google|Google]]** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK_MEMBERS`. Board member. - **HR-1592 — `includes` → [[wiki/HPE|HPE]]** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK_MEMBERS`. Board member. - **HR-1593 — `includes` → [[wiki/Intel|Intel]]** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK_MEMBERS`. Board member. - **HR-1594 — `includes` → [[wiki/Meta|Meta]]** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK_MEMBERS`. Board member. - **HR-1595 — `includes` → [[wiki/Microsoft|Microsoft]]** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK_MEMBERS`. Board member. - **HR-1596 — `includes` → [[wiki/Synopsys|Synopsys]]** — **VERIFIED EXTERNAL**; evidence `WEB_UALINK_MEMBERS`. Board member. - **HR-1597 — `cross_threads` → [[wiki/Infrastructure Ecology|Infrastructure Ecology]]** — **ANALYTIC CONVERGENCE**; evidence `WEB_UALINK_MEMBERS`, `WIKI_ARCHIVE`. Competitors coordinate on common accelerator-memory/interconnect substrate. #### Incoming typed edges - **HR-0275 — [[wiki/AI Factory|AI Factory]] `wiki_links_to` → this entry** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `AI Factory.md`. - **HR-0299 — [[wiki/CXL|CXL]] `wiki_links_to` → this entry** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `CXL.md`. - **HR-0872 — [[wiki/Optical Fabric|Optical Fabric]] `wiki_links_to` → this entry** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `Optical Fabric.md`. - **HR-0925 — [[wiki/Rack-Scale Computing|Rack-Scale Computing]] `wiki_links_to` → this entry** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `Rack-Scale Computing.md`. - **HR-1163 — [[wiki/Ultra Ethernet|Ultra Ethernet]] `wiki_links_to` → this entry** — **EXISTING WIKI EDGE**; evidence `WIKI_ARCHIVE`. Direct internal link currently present in `Ultra Ethernet.md`. - **HR-1333 — [[wiki/Composable Infrastructure|Composable Infrastructure]] `should_crosslink_with` → this entry** — **RESEARCH CANDIDATE**; evidence `WIKI_ARCHIVE`.   ### Research Candidates - **R-002435 — research candidate:** Assess whether **UALink** and [[wiki/Composable Infrastructure|Composable Infrastructure]] warrant reciprocal reader-facing prose. Settlement requires a source that documents the relationship directly. Suggested missing reciprocal/cross-thread edge. Shared internal mediators (3): AI Factory, CXL, Rack-Scale Computing  ## Research Inferences  These entries translate the forward-looking register in [[research/Research Inferences|Research Inferences]] into ordinary wiki prose. The tier labels apply to the inference, not automatically to every factual anchor inside it. The interpretive frame comes from [[articles/Technologies for Consciousness Mapping and Transfer|Technologies for Consciousness Mapping and Transfer]] and [[articles/Mind Uploading and AI — The Host is Reusable and the Person is the Delta|Mind Uploading and AI — The Host is Reusable and the Person is the Delta]]. Collection route: [[collections/Neurotech|Neurotech]]. - **INF-0190 — Strongly indicated.** Open scale-up interconnect standards let accelerators from multiple vendors share a coherent domain, breaking single-vendor lock at the fabric layer. Open fabric is the precondition for a hosted-state market with more than one possible host.